The copper (Cu) damascene method has become mainstream in the manufacture of copper interconnects in microminiaturized integrated circuits (IC). Currently, chemical mechanical polishing (CMP) of the copper layers causes dishing of the copper interconnects. This dishing causes reduced yields, reliability and unacceptable performance. The deleterious effects of dished copper interconnects accumulate interconnect level by interconnect level.
U.S. Pat No. 5,723,387 to Chen discloses a self-contained unit for forming copper metallurgy interconnection structures on semiconductor (SC) substrates that provides a way of reducing the number of times the wafer is transferred between the less environmentally clean wet process steps and very clean dry process steps. The copper may be deposited over and into a barrier layer lined substrate surface and groove by electroless and electroplating techniques. The copper layer is then polished to expose the barrier layer which is then etched away. The copper is then polished to planarize it with the substrate surface and a second barrier layer is selectively deposited on the copper by electroless plating techniques. After cleaning and drying, a second dielectric layer is applied and the steps are repeated to form additional metallurgy layers.
U.S. Pat. No. 5,308,796 to Feldman et al. discloses a selective copper plating process where palladium silicide is used as a catalytic surface. Copper plating is introduced only where the silicide is present.
U.S. Pat. No. 5,298,058 to Matsui et al. discloses an electroless copper plating bath comprising a water soluble copper salt, a complexing agent, and a reducing agent consisting of phosphorous acid or a phosphite. The bath is less expensive than conventional plating baths using hypophosphorous acid.
U.S. Pat. No. 5,603,768 to Yoon et al. discloses an apparatus using flow-inducing panels for electroless copper plating of complex plastic microwave assemblies.
U.S. Pat. No. 5,695,810 to Dubin et al. discloses a CoWP barrier layer and electroless copper interconnect processes.
U.S. Pat. No. 5,674,787 to Zhao et al. discloses an electroless copper deposition technique to form interconnects that does not require CMP to planarize the plug surface after selective formation of the plug in the via opening.